1. Field of the Invention
The present invention relates to a stacking semiconductor device, in which semiconductor devices each having a semiconductor element provided thereon are stacked in at least two or more layers and three-dimensionally mounted, and a production method of the stacking semiconductor device.
2. Description of the Related Art
In recent years, the miniaturization of digital equipments, such as a digital still camera and a digital camcorder, has advanced and three-dimensional mounting which enables respective components to be mounted in a more space-saving manner is drawing attention. As the three-dimensional mounting, there have been known a stacked chip type in which semiconductor elements are stacked in two or more layers as a chip size package (CSP) and a ball grid array (BGA) and a stacking semiconductor device in which semiconductors are stacked in two or more layers.
FIG. 7 shows a stacked chip type semiconductor package, and a large semiconductor element 52 and a small semiconductor element 53 are provided on a wiring board 51 by sequential stacking. The wiring board 51 and the semiconductor elements 52, 53 are electrically connected to each other by wire bonds 54. The semiconductor elements 52, 53 and the wire bonds 54 are encapsulated with an encapsulant resin 55.
In recent years, stacking semiconductor devices disclosed in Japanese Patent Application Laid-Open Nos. 2004-281919 and 2004-335603, and the like are attracting lots of attention. A general stacking semiconductor device is shown in FIG. 8. On a wiring board 121 is mounted a semiconductor element 122 via an ACF resin 124. On a semiconductor device 102 constituted by the wiring board 121 and the semiconductor element 122, there is stacked a semiconductor device 103, in which a wiring board 131 having a semiconductor element 132 mounted thereon is encapsulated with an encapsulant resin 133. A land 123 on a front surface of the semiconductor device 102 and a land 133 on a rear surface of the semiconductor device 103 are bonded to each other by an external connection terminal (solder ball) 111. That is, the semiconductor device 102 and the semiconductor device 103 are electrically connected to each other by the solder ball 111. Further, on a rear surface of the wiring board 121 are provided a plurality of lands 125, and an external connection terminal (solder ball) 112 is attached to each of the lands 125.
FIGS. 9A, 9B and 9C are cross-sectional views which show the bonding steps of the semiconductor device 102 and semiconductor device 103 which constitute the stacking semiconductor device shown in FIG. 8. First, as shown in FIG. 9A, a flux 123a is supplied onto the land 123 on the front surface of the semiconductor device 102. Next, the semiconductor device 103 is mounted on the semiconductor device 102 via the solder balls 111. Incidentally, the solder balls 111 are bonded beforehand to the rear surface of the semiconductor device 103. With the semiconductor device 103 being mounted on the semiconductor device 102, the semiconductor device 102 and the semiconductor device 103 are subjected to a reflow process, whereby the solder ball 111 and the land 123 are bonded to each other. Next, as shown in FIG. 9B, solder balls 112 are bonded to the rear surface of the semiconductor device 102. The stacking semiconductor device thus completed is mounted on a mother board 104 as shown in FIG. 9C.
However, in a semiconductor device, warpage will occur readily due to a difference in coefficient of thermal expansion between a wiring board and a semiconductor element, which are constituent members of the semiconductor device, or a difference in modulus of elasticity between the respective constituent members. The mechanism of occurrence of warpage is described below by taking a general semiconductor device as an example. FIGS. 1A, 10B and 10C show a general semiconductor device in which a semiconductor element 122 is mounted on a wiring board 121 via an AFC resin 124. Usually, a semiconductor device warps in a convex manner with the semiconductor element 122 facing upward, as shown in FIG. 1A, due to differences in coefficient of linear expansion of the wiring board 121, the ACF resin 124 and the semiconductor element 122. The warpage occurs due to differences in coefficient of thermal expansion generated when the semiconductor device 102 goes through a heating step during the production process thereof. The amount of the warpage depends on the specifications of the respective constituent members. However, for example in a case where the thickness of the wiring board 121 is 0.4 to 0.5 mm, the thickness of the semiconductor element 122 is 0.1 to 0.2 mm and the size of the semiconductor device 102 is 10 to 15 mm, it has been confirmed that the wiring board 121 warps by about 40 to 50 μm.
The amount and direction of warpage of the wiring board 121 will vary depending on the heating temperature. That is, in a case where the wiring board 121 warps by 40 to 50 μm in the convex manner, as shown in FIG. 1A, at room temperature (23° C.), the wiring board 121 will warp by 20 to 30 μm in the reverse direction, i.e., in a concave manner as shown in FIG. 10C, at 220° C. which is a solder melting temperature.
FIGS. 11A, 11B and 11C show the state of formation of a stacking semiconductor device 1 by bonding a semiconductor device 103 onto such a semiconductor device 102.
First, as shown in FIG. 11A, the semiconductor device 103 is mounted on the semiconductor device 102 which warps by 40 to 50 μm in such a convex manner as to protrude toward the semiconductor element 122 side. Next, when heated up to 220° C. by a reflow process for melting solder balls 111, the wiring board 121 warps by 20 to 30 μm in a concave manner as shown in FIG. 11B. Furthermore, when the stacking semiconductor device 1 is cooled, the wiring board 121 will return to the convex shape shown in FIG. 11A. However, because the end portions restrained by the solder balls 111 are not deformed, the wiring board 121 will come to have a shape of letter W as shown in FIG. 11C. The stacking semiconductor device 1 having such a shape will pose the problem of co-planarity in the step of mounting on a mother board to generate bonding failures.
That is, as shown in FIG. 12, when the stacking semiconductor device 1 is mounted on the mother board 104, the solder balls 112 on the inner side of the wiring board 121 do not come into contact with the lands 141 of the mother board 104. For this reason, even when the solder melts, the balls 112 are not bonded to the mother board 104, thereby generating a connection failure.
Further, when heat is applied to the wiring board 121 of the stacking semiconductor device 1 by a reflow process or the like, the semiconductor device 102 is deformed from the letter W shape to a concave shape. At this time, if the amount of deformation of the wiring board 121 is large, the solder balls 112 just under the semiconductor element 122 are crushed and adjacent solders may come into contact with each other to cause short circuiting. Moreover, in the peripheral portions, the distance between the wiring board 121 and the mother board 104 increases and the solder is stretched, with the result that a connection failure may sometimes occur.
It has been ascertained that the amount of the warpage of the wiring board 121 becomes approximately double when the thickness of the wiring board becomes half. Therefore, with the size of a semiconductor device becoming smaller, the influence of the warpage of a wiring board increases. Particularly, in a stacking semiconductor device, miniaturization has advanced and the problem of warpage has become prominent.
Japanese Patent Application Laid-Open No. 2004-335603 discloses a stacking semiconductor device in which an adhesive 125 is interposed between a semiconductor device 102 and a semiconductor device 103, as shown in FIGS. 14A to 14C. The purpose of the interposition of the adhesive 125 is to accurately align the semiconductor device 102 and the semiconductor device 103 and to suppress peeling between the semiconductor devices. For this reason, the adhesive 125 needs to be cured after the solidification of the solder balls 111. Therefore, as the adhesive 125, a thermoplastic adhesive which does not cure during the reflow process of the solder and cures after the reflow is used.
However, in the stacking semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2004-335603, it is not possible to suppress the warpage of a wiring board 121 which occurs during the reflow process for melting the solder. That is, when the semiconductor device 103 is mounted on the semiconductor device 102, the semiconductor device 102 warps in a convex manner, with the semiconductor element 122 facing upward. Further, when heated and subjected to the reflow process, the wiring board 121 warps in a concave manner as shown in FIG. 14A, because the adhesive 125 is not yet cured at this time. Next, the semiconductor device 102 is cooled and the adhesive 125 cures at a prescribed temperature. However, at this time, the wiring board 121 has already been deformed to have a shape of letter W as shown in FIG. 14B. Therefore, the problems of connection failure and short circuiting described above with reference to FIGS. 12 and 13 arise.